Particular embodiments generally relate to parallel simulation of a design under test.
In the design of electronic devices, such as integrated circuits, a design is simulated to test whether it operates correctly. A model of the design may be described using a hardware description language (HDL), such as Verilog®.
To speed up simulation, a parallel simulation system may be used that simulates the design in parallel. Because the simulation is being performed in parallel, access to memory values shared by different simulations being performed in parallel is controlled. This is because one thread may access data memory values that may be wrong if access to the data memory is not controlled. Thus, when a thread accesses a data memory location, a semaphore may be used to lock the data memory location. Accordingly, other threads cannot access the data memory location. This slows down simulation as some threads may not be able to continue the simulation process while the data memory location is locked. Accordingly, the purpose of providing a faster simulation using multiple threads may be defeated because of the use of a semaphore to lock data memory locations may slow down the simulation.